This invention relates to a computer operated system for designing integrated circuits and specifically systems which derive a hierarchical interconnection net list from an integrated circuit data base and provide net functional descriptions for all hierarchical blocks and components in the circuit.
A circuit designer initially creates a logic circuit, which may include hundreds of different logic components, and which is later fabricated into a microelectronic chip (IC). To manufacture an integrated circuit chip requires the circuit schematic diagram be transformed into a format for producing, by computer controlled processes, a silicon wafer containing metallization patterns which form the circuit's logic elements. Such transformation includes the use of a computer aided design (CAD) workstation having a plurality of component libraries, each library defining a family of components of given properties, e.g., delay times, fabrication technology, and so on.
A component library includes a list of all components that are available to a designer. The components in each library are identified by the generic description of the component type. For example, the term "NAND" for a NAND gate is its type description and distinguishes this component from others such as OR gates, flip-flops, and so on. A two-input NAND gate might be a type 2NAND. When a particular 2NAND component is placed in a given circuit design, it is given an instance name, to distinguish it from all other 2NAND gates in the circuit.
A group of components which perform a given function, i.e., a block, and blocks which are closely electrically related, should be placed as close as possible to one another to conserve wafer real estate and simplify conductor routing. The placement of components and the routing of the conductors is done by computer software at a later stage in the wafer fabrication process. Once an initial block of components is created, the CAD workstation can be used to duplicate such blocks which are then interconnected by the designer on the workstation display to form more complex circuits. A block in a given circuit level may be subdivided into a plurality of subordinate functional blocks. The subordinate blocks may be further subdivided into other more subordinate blocks and so on until the circuit's most primitive subordinate level is represented by components. In practice, the designer may start with components and build the circuit from the components or start from the most general block diagram and work down toward the component level. Blocks are given a type designation and an instance name when they are created.
The term "part" as used herein refers to either a subordinate block or a component. The most superior block in the circuit is referred to as a "top" and every other block is subordinate to it. The arrangement of a circuit by block diagram at different levels is referred to as a hierarchy and the hierarchy is important for transferring the circuit design onto a silicon wafer because it identifies the most immediate next of kin of a given block. The next of kin identification is used by subsequent operations for placement and routing and test purposes.
The creation of the circuit on the workstation display, known as "schematic capture," also includes naming the interconnecting wires of the different blocks and components. These interconnecting wires are referred to as "nets." Nets, whether at the block or component level, are designated by functional description and name. The functional description indicates whether a net is an input, an output, or bidirectional with respect to the component it is attached to. During schematic capture, the complete functional block layout of a given circuit at each level is entered on the workstation including the part names and type, and the net names. However, net functional descriptions are available only relative to components and only from the component libraries and are not designated by such a description in the schematic capture circuit layout.
After entering a circuit design on the workstation, certain other processes are required to create the silicon wafer fabrication data. One such process employs a logic simulator which simulates, for a given logic circuit and a given logic input, the resultant logic output. This simulation is an essential step needed to verify the accuracy of the logic design. This process, however, needs to know all block functions and their net functional descriptions. Another process is one employed for placing the components on the silicon wafer in a given layout and for routing the conductors among the components on the wafer. This latter process needs to know which blocks are adjacent in hierarchy order to optimize the layout and routing.
However, a problem arises in the use of certain CAD workstations with certain logic simulators and placement and routing computer programs. Certain of such simulation software and placement and routing programs requires a hierarchical net list describing a given circuit design. A hierarchical net list, shown in TABLE II herein, is a list of all blocks and components, their names and types, and the names and functional descriptions of their primary nets in hierarchical order. Starting with the top block, the hierarchical net list includes the instance names for each subordinate block, its type and the components, if any, connected to its subordinate blocks, and the names and the functional descriptions of all primary nets for each block.
Some CAD workstations automatically create such hierarchical net lists from the schematic capture stage. However, not all commercially available CAD workstations implement such hierarchical net lists. Those systems manufacturers who have workstations which do not have the capability for generating hierarchical net lists cannot as easily use their circuit designs already created on their CAD workstations for IC manufacture and must repeat the design transfer process to a workstation with hierarchical net list capability or manually enter a hierarchical net list. This is costly and cumbersome.